Register transfer

ํ•œํ•™๊ธฐ๋™์•ˆ ๋ฐฐ์šธ๊ฒƒ

  • ๋ ˆ์ง€์Šคํ„ฐ ์ข…๋ฅ˜์™€ ์“ฐ์ž„ (ํ•˜๋“œ์›จ์–ด)
  • ์‹œํ€€์Šค (์†Œํ”„ํŠธ์›จ์–ด)
  • ์ปจํŠธ๋กค (์ปจํŠธ๋กค)

Block Diagram of Register

  • AR (Address Register)
  • DR(Data Register) or BR(Buffer Register)
  • IR(Instruction Register)
  • PC(Program Counter)
  • R0 ~ R15 or A ~ H.

RTL, Basic symbols for register transfer

  • Register-transfer level
    • ํ•˜๋“œ์›จ์–ด ๋ ˆ์ง€์Šคํ„ฐ ๊ฐ„์˜ ๋””์ง€ํ„ธ ์‹ ํ˜ธ ํ๋ฆ„๊ณผ ํ•ด๋‹น ์‹ ํ˜ธ์— ๋Œ€ํ•ด ์ˆ˜ํ–‰๋˜๋Š” ๋…ผ๋ฆฌ ์—ฐ์‚ฐ ์ธก๋ฉด์—์„œ ๋™๊ธฐ์‹ ๋””์ง€ํ„ธ ํšŒ๋กœ๋ฅผ ๋ชจ๋ธ๋งํ•˜๋Š” ์„ค๊ณ„ ์ถ”์ƒํ™”์ž…๋‹ˆ๋‹ค.
  • Symbol: Microoperation์„ ํ™œ์šฉํ•œ ๋ฐ์ดํ„ฐ์˜ ์ด๋™์„ ๋‚˜ํƒ€๋ƒ„.
    • (ex) A <- B
    • B๋ผ๋Š” ๋ ˆ์ง€์Šคํ„ฐ์—์„œ A๋ ˆ์ง€์Šคํ„ฐ๋กœ ๋ฐ์ดํ„ฐ๋ฅผ ์˜ฎ๊ฒจ๋ผ!
    • โ€™,โ€™ : at the same time ๋™์‹œ์— ์‹œํ–‰ํ•˜๋ผ.
    • : ์ง€์ •๋œ ๋ฉ”๋ชจ๋ฆฌ์˜ ์ฃผ์†Œ
    • (ex) DR <- M[AR]
    • ๋ฉ”๋ชจ๋ฆฌ ์•ˆ์˜ AR์ด๋ผ๋Š” ์ฃผ์†Œ์— ์žˆ๋Š” ๋ฐ์ดํ„ฐ๋ฅผ DR์— ์˜ฎ๊ธด๋‹ค.
    • P : R2 <- R1
    • P ์กฐ๊ฑด์„ ๋งŒ์กฑํ•˜๋ฉด! Controlํ•œ๋‹ค๋Š” ๋œป.
    • If (P=1) then R2 <- R1
    • T๊ฐ€ 1์ผ๋•Œ R1๊ณผ R2๋ฅผ ์Šค์™€ํ•‘ํ•˜๋ผ!

BUS

  • A set of common lines
  • Bus types:
    • Address bus
    • Data bus
    • Control bus

๋ฒ„์Šค ์˜ˆ์‹œ ๊ทธ๋ฆผ (์ฑ… ์ฐธ๊ณ : Computer System Architecture - Morris Mano)

DR <- AC, AC <- DR ์ด๋•Œ ๋ฒ„์Šค๋Š” ๋ˆ„๊ฐ€ ์žก์„๊นŒ?

  • Bypass๋ผ๊ณ , DR์—์„œ AC๋กœ ์ด์–ด์ง€๋Š” ๋ผ์ธ ๋•Œ๋ฌธ์— ๋™์‹œ์ƒํ™ฉ์ผ๋•Œ AC๊ฐ€ ๋ฒ„์Šค๋ฅผ ์žก์•„์•ผํ•จ.